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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave april 2010 rev. 1.2.3 general description the xr16l2751 1 (2751) is a low voltage dual universal asynchronous receiver and transmitter (uart) with 5 volt tolerant inputs. the device includes 2 additional capabilities over the xr16l2750: intel and motorola data bus selection and a ?powersave? mode to further reduce sleep current to a minimum during sleep mode. the 2751?s register set is compatible to the st16c2550 and xr16c2850 but with added functions. it supports the exar?s enhanced features of 64 bytes of tx and rx fifos, programmable fifo tr igger level, fifo level counters, automatic hardware and software flow control, automatic rs-485 half duplex direction control, and a complete modem interface. onboard registers provide the user with operational status and data error tags. an internal loopback capability allows onboard diagnostics. independent programmable baud rate generator is provided in each uart channel to support data rates up to 6.25 mbps. n ote : 1 covered by u.s. patent #5,649,122 and #5,949,787 applications ? portable and battery operated appliances ? wireless access servers ? ethernet network routers ? cellular data devices ? telecommunication network routers ? factory automation and process controls features ? 2.25 to 5.5 volt operation ? 5 volt tolerant inputs ? functionally compatible to st16c2550 and xr16c2850 with 4 additional inputs ? intel or motorola data bus interface select ? two independent uarts up to 6.25 mbps at 5 volt, 4 mbps at 3.3 volt, and 3 mbps at 2.5 volt with 8x sampling rate 64 bytes of transmit and receive fifos transmit and receive fifo level counters programmable tx and rx fifo trigger levels automatic hardware (rts/cts) flow control selectable rts flow control hysteresis. automatic software (xoff/xon) flow control automatic rs-485 2-wire half-duplex direction control to the transceiver via rts# full modem interface infrared receive and transmit encoder/ decoder ? powersave feature reduces sleep current to 15 a at 3.3 volt ? device identification ? crystal or external clock input ? industrial and commercial temperature ranges ? 48 tqfp package (7 x 7 x 1.0 mm) f igure 1. xr16l2751 b lock d iagram xtal1 xtal2 crystal osc/buffer txa, rxa, dtra#, dsra#, rtsa#, dtsa#, cda#, ria#, op2a# intel or motorola data bus interface uart channel a 64 byte tx fifo 64 byte rx fifo brg ir endec tx & rx uart regs 2.25 to 5.5 volt vcc gnd *5 volt tolerant inputs (except xtal1) 2751blk txb, rxb, dtrb#, dsrb#, rtsb#, ctsb#, cdb#, rib#, op2b# uart channel b (same as channel a) a2:a0 d7:d0 csa# (cs#) 16/68# csb# (a3) inta (irq#) intb (logic 0) pwrsave iow# (r/w#) ior# (vcc) reset (reset#) clksel hdcntl# txrdya# txrdyb# rxrdya# rxrdyb#
f igure 2. p in o ut a ssignment 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# csa# csb# pwrsave xtal1 xtal2 iow# cdb# gnd rxrdyb# ior# dsrb# rib# rtsb# ctsb# 16/68# reset dtrb# dtra# rtsa# op2a# rxrdya# inta intb a0 a1 a2 clksel d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# hdcntl# xr16l2751 48-pin tqfp (16 mode ) vcc 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# cs# a3 pwrsave xtal1 xtal2 r/w# cdb# gnd rxrdyb# vcc dsrb# rib# rtsb# ctsb# 16/68# reset# dtrb# dtra# rtsa# op2a# rxrdya# irq# intb a0 a1 a2 clksel d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# hdcntl# xr16l2751 48-pin tqfp (68 mode ) gnd ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr16l2751cm 48-lead tqfp 0c to +70c active xr16l2751im 48-lead tqfp -40c to +85c active xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 2
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 3 pin descriptions pin description n ame 48-tqfp p in # t ype d escription data bus interface a2 a1 a0 26 27 28 i address data lines [2:0]. these 3 address lines select one of the internal registers in uart channel a/b during a data bus transaction. d7 d6 d5 d4 d3 d2 d1 d0 3 2 1 48 47 46 45 44 i/o data bus lines [7:0] (bidirectional). ior# (vcc) 19 i when 16/68# pin is high, the intel bus interface is selected and this input becomes read strobe (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an internal r egister pointed by the address lines [a2:a0], puts the data byte on the data bus to allow t he host processor to read it on the rising edge. when 16/68# pin is low, the motorola bus in terface is selected and this input is not used and should be connected to vcc. iow# (r/w#) 15 i when 16/68# pin is high, it selects intel bus interface and this input becomes write strobe (active low). the falli ng edge instigates th e internal write cycl e and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. when 16/68# pin is low, the motorola bu s interface is selected and this input becomes read (high) and write (low) signal. csa# (cs#) 10 i when 16/68# pin is high, this input is chip select a (active low) to enable channel a in the device. when 16/68# pin is low, this input becomes the chip select (active low) for the motorola bus interface. csb# (a3) 11 i when 16/68# pin is high, this input is chip select b (active low) to enable channel b in the device. when 16/68# pin is low, this input becomes address line a3 which is used for chan - nel selection in the motorola bus interface. input logic 0 selects channel a and logic 1 selects channel b. inta (irq#) 30 o when 16/68# pin is high for intel bus interf ace, this output becomes channel a inter - rupt output. the output state is defined by the user through the software setting of mcr[3]. inta is set to the active mode and op2a# output to a logic 0 when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# to a logic 1 when mcr[3] is set to a logic 0. see mcr[3]. when 16/68# pin is low for motorola bus interface, this output becomes device interrupt output (active low, open drain). an external pull-up resistor is required for proper operation.
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 4 intb 29 o when 16/68# pin is high for intel bus interf ace, this output becomes channel b inter - rupt output. the output state is defined by the user and through the software setting of mcr[3]. intb is set to the active mode and op2b# output to a logic 0 when mcr[3] is set to a logic 1. intb is set to the three state mode and op2b# to a logic 1 when mcr[3] is set to a logic 0. see mcr[3]. when 16/68# pin is low for motorola bus inte rface, this output is not used and will stay at logic zero level. leave this output unconnected. txrdya# 43 o uart channel a transmitter ready (active low). the output prov ides the tx fifo/ thr status for transmit channel a. rxrdya# 31 o uart channel a receiver ready (active low). this output provides the rx fifo/ rhr status for receive channel a. txrdyb# 6 o uart channel b transmitter ready (active low). the output prov ides the tx fifo/ thr status for transmit channel b. rxrdyb# 18 o uart channel b receiver ready (active low). this output provides the rx fifo/ rhr status for receive channel b. modem or serial i/o interface txa 7 o uart channel a transmit data or infrared encoder data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be high during reset or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is low. if it is not used, leave it unconnected. rxa 5 i uart channel a receive data or infrared receive data. normal receive data input must idle high. the infrared receiver puls es typically idles at logic 0 but can be inverted by software control prior goin g to the decoder, see mcr[6] and fctr[2]. rtsa# 33 o uart channel a request-to-send (active lo w) or general purpose output. this out - put must be asserted prior to using aut o rts flow control, see efr[6], mcr[1], fctr[1:0], emsr[5:4] and ier[6]. for auto rs485 half-duplex direction control, see fctr[3] and emsr[3]. ctsa# 38 i uart channel a clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7], msr[ 4] and ier[7]. this input should be con - nected to vcc when not used. dtra# 34 o uart channel a data-terminal-ready (act ive low) or general purpose output. dsra# 39 i uart channel a data-set-ready (active lo w) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cda# 40 i uart channel a carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. ria# 41 i uart channel a ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. op2a# 32 o output port 2 channel a - the output state is defined by the user and through the software setting of mcr[3]. wh en mcr[3] is set to a logic 1, inta is set to the level mode and op2a# output low. when mcr[3] is set to a logic 0, inta is set to the three state mode and op2a# is high. see mc r[3]. this output must not be used as a general output when the interrupt output is used else it will disturb the inta output functionality. pin description n ame 48-tqfp p in # t ype d escription
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 5 txb 8 o uart channel b transmit data or infrared encoder data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be high during reset or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is low. if it is not used, leave it unconnected. rxb 4 i uart channel b receive data or infrared receive data. normal receive data input must idle high. the infrared receiver puls es typically idles low but can be inverted by software control prior going in to the decoder, see mcr[6] and fctr[2]. rtsb# 22 o uart channel b request-to-send (active lo w) or general purpose output. this port must be asserted prior to using auto rts flow control, see efr[6], mcr[1], fctr[1:0], emsr[5:4] and ier[6]. for auto rs485 half-duplex direction control, see fctr[3] and emsr[3]. ctsb# 23 i uart channel b clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7], and ier[7]. this input should be connected to vcc when not used. dtrb# 35 o uart channel b data-terminal-ready (act ive low) or general purpose output. dsrb# 20 i uart channel b data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used . this input has no effect on the uart cdb# 16 i uart channel b carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used . this input has no effect on the uart rib# 21 i uart channel b ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. op2b# 9 o output port 2 channel b - the output st ate is defined by the user and through the software setting of mcr[3]. wh en mcr[3] is set to a logic 1, intb is set to the level mode and op2b# output low. when mcr[3] is set to a logic 0, intb is set to the three state mode and op2b# is high. see mc r[3]. this output must not be used as a general output when the interrupt output is used else it will disturb the intb output functionality. ancillary signals xtal1 13 i crystal or external clock input. this input is not 5v tolerant. xtal2 14 o crystal or buffered clock output. this output may be use to drive a clock buffer which can drive other device(s). pwrsave 12 i powersave (active high). this feature isolates the 2751?s da ta bus interface from the host preventing other bus activities that cause higher power drain during sleep mode. see sleep mode with auto wake-up and powersave feature section for details. 16/68# 24 i intel or motorola bus select. when 16/68# pin is high, 16 or intel mode, the device will operate in the intel bus type of interface. when 16/68# pin is low, 68 or motorola mo de, the device will operate in the motor - ola bus type of interface. clksel 25 i baud-rate-generator input clock prescaler sele ct for channel a and b. this input is only sampled during power up or a reset. connect to vcc for divide by 1 and gnd for divide by 4. mcr[7] can override the st ate of this pin following a reset or initializa - tion. see mcr bit-7 and figure 6 in the baud rate generator section. pin description n ame 48-tqfp p in # t ype d escription
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 6 pin type: i=input, o=output, i/o= i nput/output, od=output open drain. 1.0 product description the xr16l2751 (2751) integrates the functions of 2 enhanced 16c550 universal asynchronous receiver and transmitter (uart). its features set is compatible to the xr16l2750 and xr16c2850 devices but offers intel or motorola data bus interface and powersave to isolate the data bus interface during sleep mode. hence, the 2751 adds 4 more inputs : 16/68#, pwrsave, hdcntl# and clksel pins. each uart is independently controlled having its own set of device configuration regi sters. the configuration registers set is 16550 uart compatible for control, status and data transfer. additi onally, each uart channel has 64-bytes of transmit and receive fifos, automatic rt s/cts hardware flow control with hyster esis control, automatic xon/xoff and special character software flow control, programmable transmit and receive fifo trigger levels, fifo level counters, infrared encoder and decoder (irda ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4. the xr16l2751 can operate from 2.25v to 5.5v with 5 volt tolerant inputs. the 2751 is fabricated with an advanced cmos process. enhanced features the 2751 duart provides a solution that supports 64 byte s of transmit and receive fifo memory, instead of 16 bytes in the st16c2550, or one byte in the st16c2450. the 2751 is designed to work with low supply voltage and high performance data communication systems, that require fast data processing time. increased performance is realized in the 2751 by the larger transm it and receive fifos, fifo trigger level control, fifo level counters and automatic flow control mechanism. this allows the external processor to handle more networking tasks within a given time. for example, the st16c2550 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a character l ength of 11 bits, including start/stop bits at 115.2 kbps). this means the external cpu will have to service the receive fifo at 1.53 ms intervals. however with the 64 byte fifo in the 27 51, the data buffer will not re quire unloading/loading for 6.1 ms. this increases the service interval giving the external cpu additional ti me for other applications and reducing the overall uart interrupt servicing time. in addition, the programmable fifo level trigger interrupt and automatic hardware/ software flow control is uniquely provided for maximum data th roughput performance especially when operating in a multi-channel system. the combinatio n of the above greatly reduces the cpu?s bandwidth requirement, increases performance, and reduces power consumption. the 2751 supports a half-duplex output direction control signaling pin, rts# a/b, to enable and disable the external rs-485 transceiver operation. it automatically s witches the logic state of the output pin to the receive state after the last stop-bit of the last character has been shifted out of the transmitter. after receiving, the logic state of the output pin switches back to the transmit st ate when a data byte is loaded in the transmitter. the hdcntl# 37 i auto rs-485 half-duplex direction output enable for channel a and b (active low). connect this pin to vcc for normal rts# a/b function and to gnd for auto rs-485 half-duplex direction output via the rts# a/ b pins. rts# output goes low for transmit and high for receive (polarity inversion is available via emsr[3]). fctr[3] in channel a and b have control only if this input is disabled or at vcc. reset (reset#) 36 i when 16/68# pin is high for intel bus interface, this input becomes reset (active high). when 16/68# pin is low for motoro la bus interface, this input becomes reset# (active low). a 40 ns minimum active pulse on this pin will reset the internal registers and all out - puts of channel a and b. the uart transmi tter output will be held high, the receiver input will be ignored and outputs are reset during reset period (see uart reset con - ditions). vcc 42 pwr 2.25v to 5.5v power supply. all input pins, except xtal1, are 5v tolerant. gnd 17 pwr power supply common, ground. pin description n ame 48-tqfp p in # t ype d escription
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 7 auto rs-485 direction control pin is no t activated after reset. to activate the direction control function, user has to set fctr[3] = 1. this pin is normally high for receive state, low for transmit state. data bus interface, intel or motorola type the 2751 provides a single host interface for the 2 ua rts and supports intel or motorola microprocessor (cpu) data bus interface. the intel bus compatible interf ace allows direct interconnect to intel compatible type of cpus using ior#, iow# and csa# or csb# inputs for data bus operation. the motorola bus compatible interface instead uses the r/w#, cs# and a3 signals for data bus transactions. few data bus interface signals change their functions depending on user?s selection, see pin description for details. the intel and motorola bus interface selection is made th rough the pin, 16/68#, pin 24. data rate each channel in the 2751 is capable of operation up to 3.125 mbps at 5v, 2 mbps at 3.3v and 1 mbps at 2.5v supply with 16x internal samp ling clock rate, and 6.25 mbps at 5v, 4 mbps at 3.3v and 2 mbps at 2.5v with 8x sampling clock rate. the device can operate with an exte rnal 24 mhz crystal on pins xtal1 and xtal2, or external clock source of up to 50 mhz on xtal1 pin. with a typical crystal of 14.7456 mhz and through a software option, the user can set the presca ler bit for data rates of up to 1.84 mbps. internal enhanced register sets each uart has a set of enhanced registers providing c ontrol and monitoring functions for interrupt enable/ disable and status, fifo enable/disable, programmable tx and rx fifo trigger leve l, tx and rx fifo level counters, automatic hardware/software flow control en able/disable with selectable hysteresis, automatic rs- 485 half-duplex direction control output enable/disable, programmable baud rates, infrared encoder/decoder enable/disable, modem interface controls and status, and sleep mode are all standard features. following a power on reset or an external reset (and operating in 16 or intel mode), the registers defaults to the reset condition and its is compatible with previous generation of uarts, 16c450, 16c550, 16c650a and 16c850.
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 8 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the 2751 data interface supports the in tel compatible types of cpus and it is compatible to the industry standard 16c550 uart. no clock (oscillator nor external clock) is requir ed to operate a data bus transaction. each bus cycle is asynchronous using cs a/b#, ior# and iow# or cs#, r/w# and a3 inputs. both uart channels share the same data bus for host operations. a typical data bus interconnection for intel and motorola mode is shown in figure 3 . f igure 3. xr16l2751 t ypical i ntel /m otorola d ata b us i nterconnections vcc vcc op2a# dsra# ctsa# rtsa# dtra# rxa txa ria# cda# op2b# dsrb# ctsb# rtsb# dtrb# rxb txb rib# cdb# gnd a0 a1 a2 uart_csa# uart_csb# ior# iow # d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow # uart channel a uart channel b uart_intb uart_inta intb inta rxrdya# txrdya# rxrdya# txrdya# rxrdyb# txrdyb# rxrdyb# txrdyb# uart_reset reset serial interface of rs-232, rs-485 serial interface of rs-232, rs-485 2750_int intel data bus interconnections (no connect) (no connect) 2.25 to 5.5 volt vcc vcc op2a# dsra# ctsa# rtsa# dtra# rxa txa ria# cda# op2b# dsrb# ctsb# rtsb# dtrb# rxb txb rib# cdb# gnd a0 a1 a2 uart_cs# a3 r/w# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_irq# intb inta rxrdya# txrdya# rxrdya# txrdya# rxrdyb# txrdyb# rxrdyb# txrdyb# reset# rs-232 serial interface rs-232 serial interface motorola data bus interconnections vcc uart_reset# (no connect) (no connect) (no connect) vcc
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 9 2.2 5-volt tolerant inputs the 2751 can accept up to 5v inputs when operating at 3. 3v or 2.5v. but note that if the 2751 is operating at 2.5v, its v oh may not be high enough to meet the requirements of the v ih of a cpu or a serial transceiver that is operating at 5v. caution: xtal1 is not 5 volt tolerant. 2.3 device hardware reset the reset or reset# input resets the internal registers and the serial in terface outputs in both channels to their default state (see table 17 ). an active pulse of long er than 40 ns duration will be required to activate the reset function in the device. 2.4 device identification and revision the xr16l2751 provides a device identification code and a device revision code to distinguish the part from other devices and revisions. to read the identification code from the part, it is required to set the baud rate generator regist ers dll and dlm both to 0x00. now reading the content of the dlm will provide 0x0a for the xr16l2751 and read ing the content of dll will provide the revision of the part; for exampl e, a reading of 0x01 means revision a. 2.5 channel a and b selection the uart provides the user with the capability to bi-directionally tr ansfer information be tween an external cpu and an external serial communication device. during intel bus mode (16/68# pin connected to vcc), a logic 0 on chip select pins, csa# or csb#, allows the us er to select uart channel a or b to configure, send transmit data and/or unload receive data to/from the ua rt. selecting both uarts can be useful during power up initialization to write to the same internal registers, but do not attempt to read from both uarts simultaneously. individual channel select functions are shown in table 1 . t able 1: c hannel a and b s elect in 16 m ode f unction 1 1 uart de-selected 0 1 channel a selected 1 0 channel b selected 0 0 channel a and b selected during motorola bus mode (16/68# pin connected to gnd), the package interface pins are configured for connection with motorola, and other popular microproce ssor bus types. in this mode the 2751 decodes an additional address, a3, to select one of the uart ports. the a3 address decode function is used only when in the motorola bus mode. see table 2 . t able 2: c hannel a and b s elect in 68 m ode f unction 1 n/a uart de-selected 0 0 channel a selected 0 1 channel b selected 2.6 channel a and b internal registers each uart channel in the 2751 has a set of enhanced registers for control, monitoring and data loading and unloading. the configuration register set is compatib le to those already available in the standard single 16c550 and dual st16c2550. these r egisters function as data holding regi sters (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and control registers, (lsr/ lcr), modem status and control regist ers (msr/mcr), programmable data rate (clock) divisor registers (dll/ dlm), and an user accessible scratchpad register (spr). csa# csb# cs# a3
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 10 beyond the general 16c25 50 features and capabilitie s, the 2751 offers enhanced feature registers (efr, xon/ xoff 1, xon/xoff 2, fctr, trg, emsr, fc) that prov ide automatic rts and cts hardware flow control, xon/ xoff software flow control, automatic rs-485 half-dup lex direction output enable/di sable, fifo trigger level control and fifo level counters. all the register functions are discussed in full detail later in ?section 3.0, uart internal registers? on page 22 . 2.7 dma mode the device does not support direct me mory access. the dma mode (a legacy term) in this document doesn?t mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# a/b and txrdy# a/b output pins. the transmit and receive fifo trigger levels provide additional flexibility to the user for block mode operation. the lsr bits 5- 6 provide an indication when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3 = 1). when the tran smit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the 2751 is placed in single-character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the programmed trigger level. in this mode, the 2751 sets the txrdy# pin when the transmit fifo becomes fu ll, and sets the rxrdy# pin when the receive fifo becomes empty. the following table shows their behavior. also see figures 20 through 25 . t able 3: txrdy# and rxrdy# o utputs in fifo and dma m ode p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr b it -3 = 0 (dma m ode d isabled ) fcr b it -3 = 1 (dma m ode e nabled ) rxrdy# a/b low = 1 byte. high = no data. low = at least 1 byte in fifo. high = fifo empty. high to low transition when fifo reaches the trigger level, or time-out occurs. low to high transition when fifo empties. txrdy# a/b low = thr empty. high = byte in thr. low = fifo empty. high = at least 1 byte in fifo. low = fifo has at least 1 empty location. high = fifo is full. 2.8 inta and intb outputs the inta and intb interrupt output changes according to the operating mode and enhanced features setup. table 4 and 5 summarize the operating behavior for the transmitter and receiver. also see figures 20 through 25 . t able 4: inta and intb p ins o peration for t ransmitter a uto rs485 m ode fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin no low = a byte in thr high = thr empty low = fifo above trigger level high = fifo below trigger level or fifo empty inta/b pin yes low = a byte in thr high = transmitter empty low = fifo above trigger level high = fifo below trigger level or transmitter empty t able 5: inta and intb p in o peration f or r eceiver fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin low = no data high = 1 byte low = fifo below trigger level high = fifo above trigger level
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 11 2.9 crystal oscillator or external clock input the 2751 includes an on-chip oscillator (xtal1 and xt al2) to produce a clock for both uart sections in the device. the cpu data bus does not require this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer i nput with xtal2 pin being the output. pleas e note that the i nput xtal1 is not 5v tolerant and so the maximum voltage at the pin should be vcc. for programming details, see ?programmable baud rate generator.? f igure 4. t ypical oscillator connections c1 22-47pf c2 22-47pf y1 1.8432 mhz to 24 mhz r1 0-120 (optional) r2 500k - 1m xtal1 xtal2 the on-chip oscillator is designed to use an industry stand ard microprocessor cryst al (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connected externally between the xtal1 a nd xtal2 pins (see figure 5). the programmable baud rate generator is capable of operating with a crystal osc illator frequency of up to 24 mhz. however, with an external clock input on xtal1 pin and a 2k ohms pull-up resistor on xtal2 pin (as shown in figure 5 ) it can extend its operation up to 50 mhz (6.25 mbps serial data rate) at 5v with an 8x sampling rate. f igure 5. e xternal c lock c onnection for e xtended d ata r ate 2k xtal1 xtal2 r1 vcc external clock vcc gnd for further reading on the oscillator circuit please see the applicat ion note dan108 on the exar web site at http://www.exar.com.
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 12 2.10 programmable baud rate generator each uart has its own baud rate generator (brg) with a pr escaler. the prescaler is controlled by clksel hardware pin or a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4 and can override the clksel pin following rese t. the clock output of the prescaler goes to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 - 1) to obtain a 16x sampling rate clock of the serial data rate. the sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor defaults to the maximum baud rate (dll = 0x01 and dlm = 0x00) upon power up. f igure 6. b aud r ate g enerator and p rescaler xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x sampling rate clock to transmitter baud rate generator logic programming the ba ud rate generator regi sters dlm and dll provides th e capability of selecting the operating data rate. table 6 shows the standard data rates availabl e with a 14.7456 mhz crystal or external clock at 16x sampling rate clock rate. a 16x sampling clock is typically used . however, user can select the 8x sampling clock rate mode (emsr bit-7=0) to double the operating data rate. when using a non-standard data rate crystal or external clock, the divisor value can be calculated for dll/dlm with the following equation. divisor (decimal) = (xtal1 clock frequency / prescaler) / (ser ial data rate x 16), with 16xmode [emsr bit-7] = 1 divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 8), with 16xmode [emsr bit-7] = 0 t able 6: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 ( default ) d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) p rogram v alue (hex) p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0 dlm dll
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 13 2.11 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 64 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x/8x internal clock. a bit time is 16 (8) clock periods (see emsr bit-7). the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabl ed, and adds the stop-bit(s). the status of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.11.1 transmit holding re gister (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 64 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.11.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. f igure 7. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x clock (emsr bit-7) 2.11.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 64 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trig ger level. the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty.
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 14 f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x or 8x clock (emsr bit-7) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg. txfifo1 2.12 receiver the receiver section contains an 8-bit receive shift register (rsr) and 64 bytes of fifo which includes a byte-wide receive holding register (rhr ). the rsr uses the 16x/8x clock (e msr bit-7) for timing. it verifies and validates every bit on the incoming character in the middle of each data bi t. on the falling edge of a start or false start bit, an internal receiver c ounter starts counting at the 16x/8x clock rate. after 8 clocks (or 4 if 8x) the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr re gister bits 2-4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the erro r tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo tr igger level. furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not re ceived for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.12.1 receive holding regi ster (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 64 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains the first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4.
f igure 9. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x or 8x clock (emsr bit-7) receive data characters data bit validation error tags in lsr bits 4:2 f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x clock error tags (64-sets) error tags in lsr bits 4:2 64 bytes by 11-bit wide fifo receive data characters fifo trigger=16 example: - rx fifo trigger level selected at 16 bytes (see note below) data fills to 24 data falls to 8 data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1. xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 15 n ote : table-b selected as trigger table for figure 10 ( table 11 ).
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 16 2.13 auto rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 11 ): x enable auto rts flow control using efr bit-6. x the auto rts function must be started by asserting rts# output pin (mcr bit-1 to logic 1 after it is enabled). if using the auto rts interrupt: x enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin makes a transition from low to high: isr bit-5 will be set to logic 1. 2.14 auto rts hysteresis the 2751 has a new feature that provid es flow control trigge r hysteresis while maintaining compatibility with the xr16c850, st16c650a and st16c550 family of uarts. with the auto rts functi on enabled, an interrupt is generated when the receive fifo re aches the programmed rx trigger level. the rts# pin will not be forced high (rts off) until the receive fifo reaches the u pper limit of the hysteresis le vel. the rts# pin will return low after the rx fifo is unloaded to the lower limit of the hysteresis level. under the above described conditions, the 2751 will continue to accept data until th e receive fifo gets full. the auto rts function is initiated when the rts# output pin is asserted low (rts on). table 14 shows the complete details for the auto rts# hysteresis levels. please note that this tabl e is for programmable trigger levels only (table d). the hysteresis values for tables a-c are the next higher and next lower trigger levels in the corresponding table. 2.15 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 11 ): x enable auto cts flow control using efr bit-7. if using the auto cts interrupt: x enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (high): is r bit-5 will be set to 1, and uart will suspend transmission as soon as the stop bit of the character in process is shifted ou t. transmission is resumed after the cts# input is re- asserted (low), indicating more data may be sent.
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 17 f igure 11. a uto rts and cts f low c ontrol o peration rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1 the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow.
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 18 2.16 auto xon/xoff (software) flow control when software flow control is enabled ( see table 16 ), the 2751 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 charac ter value(s). if receive character(s) (rx) match the programmed values, the 2751 will halt transmission (tx) as soon as th e current characte r has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspension due to a ma tch of the xoff character, the 2751 will monitor the receive data stream for a match to the xon-1,2 character. if a match is found, the 2751 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for software flow c ontrol. different conditions can be set to detect xon/ xoff characters ( see table 16 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the 2751 compares two consecutive receiv e characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx tran smissions accordingly. under the above described flow control mechanisms, flow control charac ters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the 2751 automatically sends an xoff message (when enabled) via the serial tx output to the remote modem. the 2751 sends the xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses the programmed trigger level (for all trigger tables a-d). to clear this condition, the 2751 will transmit the programmed xon- 1,2 characters as soon as receiv e fifo is less than one trigger level below the programmed trigger level (for trigger tables a, b, and c) or when receive fifo is less than the trigger level minus the hysteresis value (for trigger tabl e d). this hysteresis value is the same as the auto rts hysteresis value in table 14 . table 7 below explains this when trigger table-b (see table 11 ) is selected. t able 7: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 8 8 8* 0 16 16 16* 8 24 24 24* 16 28 28 28* 24 * after the trigger level is reached, an xoff character is sen t after a short span of time (= time requir ed to send 2 characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting. 2.17 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the 2751 compares each incoming receive character with xoff-2 dat a. if a match exists, the received data will be transferred to fifo and is r bit-4 will be set to indicate detection of special character. al though the internal register table shows xon, xoff registers with eight bits of character information, the actual number of bits is dependent on the programmed word lengt h. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the xon, xoff registers corresponds with the ls b bit for the receive character.
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 19 2.18 auto rs485 half-duplex control the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by fctr bit-3. by default, it de-asserts rts# (high) output following the last stop bit of the last character that has been transmitted. this helps in turning around the transcei ver to receive the remote st ation?s response. when the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit fifo. the transmitter automatically re-asserts rts# (low) outpu t prior to sending the data. the rs485 half-duplex direction control output can be inverted by enabling emsr bit-3. 2.19 infrared mode the 2751 uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the irda 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide high- pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 12 below. the infrared encoder and decoder are enabled by setting mcr register bit-6 to a ?1?. when the infrared feature is enabled, the transmit data output, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero from a reset and power up, see figure 12 . typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the rx pin. each time it senses a light pulse, it returns a logic 1 to the data bit stream. however, this is not true with some infrared modules on the market which indicate a logic 0 by a light pulse. so the 2751 has a provision to invert the input polarity to accommodate this . in this case user can enable fctr bit-2 to invert the input signal. f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder - rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 20 2.20 sleep mode with wake-up indicator and powersave feature the 2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and powersave feature is included to reduce power consumption when the device is not actively used. 2.20.1 sleep mode all of these conditions must be sati sfied for the 2751 to enter sleep mode: no interrupts pending for both channels of the 2751 (isr bit-0 = 1) sleep mode of both channels are enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pins are idling high the 2751 stops its crystal oscillator to conserve power in the sleep mode . user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the 2751 resumes normal operation by any of the follo wing when powersave mode is disabled (pin 12 at ground): a receive data start bit transition (high to low) a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the sleep mode is enabled and the 2751 is awakened by one of the conditions described above, an interrupt is issued by the 2751 to signal to the cpu that it is awake. the lower nibble of th e interrupt source register (isr) will read a value of 0x1 for this interrupt and re ading the isr clears this interrupt. since the same value (0x1) is also used to indicate no pending interrupt, users should exercise caution while using the sleep mode. the 2751 will return to the sleep mode automatically after all in terrupting conditions ha ve been serviced and cleared. if the 2751 is awakened by the modem inputs , a read to the msr is required to reset the modem inputs. in any case, the sle ep mode will not be entered while an interrup t is pending from ch annel a or b. the 2751 will stay in the sleep mode of operation until it is disabled by setting ier bit-4 to a logic 0. a word of caution: owing to the star ting up delay of the crystal oscillato r after waking up from sleep mode, the first few receive characters may be lost. the number of ch aracters lost during the restart also depends on your operating data rate. more characters are lost when operati ng at higher data rate. also, it is important to keep rx a/b inputs idling high or ?mar king? condition during sleep mode to avoid receiving a ?break? condition upon the restart. this may occur when the external inte rface transceivers (rs-232, rs-485 or another type) are also put to sleep mode and cannot maintain the ?mar king? condition. to avoid this, the designer can use a 47k-100k ohm pull-up resistor on the rxa and rxb pins. 2.20.2 powersave feature if the address lines, data bus lines, iow#, ior#, csa#, csb#, and modem input lines remain steady when the 2751 is in sleep mode, the maximum current will be in the microamp range as specified in the dc electrical characteristics on page 40 . if the input lines are floating or are toggling while the 2751 is in sleep mode, the current can be up to 100 times more. if not using the po wersave feature, then an external buffer would be required to keep the address and data bus lines from to ggling or floating to achieve the low current. but if the powersave feature is en abled (pin 12 connecte d to vcc), this will eliminate the need for an external buffer by internally isolating the address, data and control signals (s ee figure 1 on page 1) from other bus activities that could cause wasteful power drain. the 2751 enters powersave mode when pin 12 is connected to vcc and the 2751 is in sleep mode (see sleep mode section above). since powersave mode isolates the address, data and control signals, the device will wake-up by: a receive data start bit transition (high to low) a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# the 2751 will return to the powersav e mode automatically afte r a read to the msr (to reset the modem inputs) and all interrupting conditio ns have been serviced and cleared. the 2751 will stay in the powersave mode of operation until it is disabled by se tting ier bit-4 to a logic 0 and/or th e powersave pin is connected to gnd.
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 21 2.21 internal loopback the 2751 uart provides an intern al loopback capability for system di agnostic purposes . the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 13 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx, rts# and dtr# pins are held hi gh or mark condition while the cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input pins must be held to a logic 1 during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. also, auto rts/cts hardware flow control is not supported during internal loopback. f igure 13. i nternal l oop b ack in c hannel a and b txa/txb rxa/rxb modem / general purpose control logic internal data bus lines and control signals rtsa#/rtsb# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) ctsa#/ctsb# dtra#/dtrb# dsra#/dsrb# ria#/rib# cda#/cdb# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc vcc op2a#/op2b#
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 22 3.0 uart internal registers each of the uart channel in the 2751 has its own set of configuration registers sele cted by address lines a0, a1 and a2 with csa# or csb# selecting the channel. the complete register set is shown on table 8 and table 9 . t able 8: uart channel a and b uart internal registers a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1, lcr 0xbf 0 0 1 dlm - div latch high byte read/write 0 0 0 drev - device revision code read-only dll, dlm = 0x00, lcr[7] = 1, lcr 0xbf 0 0 1 dvid - device identification code read-only 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only lcr 0xbf 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr 0xbf 1 0 1 lsr - line status register reserved read-only write-only 1 1 0 msr - modem status register reserved read-only write-only 1 1 1 spr - scratchpad register read/write lcr 0xbf, fctr[6] = 0 1 1 1 flvl - rx/tx fifo level counter register read-only lcr 0xbf, fctr[6] = 1 1 1 1 emsr - enhanced mode select register write-only e nhanced r egisters 0 0 0 trg - rx/tx fifo trigger level register fc - rx/tx fifo level counter register write-only read-only lcr = 0xbf 0 0 1 fctr - feature control register read/write 0 1 0 efr - enhanced function register read/write 1 0 0 xon-1 - xon character 1 read/write 1 0 1 xon-2 - xon character 2 read/write 1 1 0 xoff-1 - xoff character 1 read/write 1 1 1 xoff-2 - xoff character 2 read/write a2 a1 a0
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 23 . t able 9: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts int. enable rts int. enable xoff int. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 lcr z 0 x bf int source bit-5 int source bit-4 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set par - ity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal lopback enable op2#/int output enable rsrvd (op1#) rts# output control dtr# output control lcr z 0 x bf brg pres - caler ir mode enable xonany 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx fram - ing error rx parity error rx over - run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr z 0xbf fctr[6]=0 1 1 1 emsr wr 16x sam - pling rate mode lsr error inter - rupt. imd/dly# auto rts hyst. bit-3 auto rts hyst. bit-2 auto rs485 output inversion rsrvd rx/tx fifo count bit-1 rx/tx fifo count bit-0 lcr z 0 x bf fctr[6]=1 1 1 1 flvl rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 24 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 14. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 13. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive inte rrupts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr z 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 drev rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr z 0xbf dll=0x00 dlm=0x00 0 0 1 dvid rd 0 0 0 0 1 0 1 0 enhanced registers 0 0 0 trg wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr=0 x bf 0 0 0 fc rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 fctr rd/wr rx/tx mode scpad swap trig ta b l e bit-1 trig ta b l e bit-0 auto rs485 direction control rx ir input inv. auto rts hyst bit-1 auto rts hyst bit-0 0 1 0 efr rd/wr auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4] , mcr[7:5 ] soft- ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 1 0 0 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 9: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 25 b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the xr16l2751 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data characte r in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. x logic 0 = disable the receive data ready interrupt (default). x logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when data in the fifo fa lls below the programmed trigger level in the fifo mode. if the thr is empty when this bit is enabled , an interrupt will be generated. x logic 0 = disable transmit ready interrupt (default). x logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bits 2-4 generate an in terrupt when the character with errors is read out of the fifo (default). instead, lsr bits 2-4 can be prog rammed to generate an interrupt immediately, by setting emsr bit-6 to a logic 1. x logic 0 = disable the receiver line status interrupt (default). x logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable x logic 0 = disable the modem status register interrupt (default). x logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) x logic 0 = disable sleep mode (default). x logic 1 = enable sleep mode. see sleep mode section for further details. ier[5]: xoff interrupt enable (requires efr bit-4=1) x logic 0 = disable the software flow cont rol, receive xoff interrupt. (default) x logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details.
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 26 ier[6]: rts# output interrupt enable (requires efr bit-4=1) x logic 0 = disable the rts# interrupt (default). x logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high. ier[7]: cts# input interrupt enable (requires efr bit-4=1) x logic 0 = disable the cts# interrupt (default). x logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt le vel to be serviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 10 , shows the data values (bit 0-5) for the inte rrupt priority levels an d the interr upt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: x lsr is by any of the lsr bits 1, 2, 3 and 4. x rxrdy is by rx trigger level. x rxrdy time-out is by a 4-char plus 12 bits delay timer. x txrdy is by tx trigger level or tx fifo empty (or transmitter empty in auto rs-485 control). x msr is by any of the msr bits 0, 1, 2 and 3. x receive xoff/special character is by det ection of a xoff or special character. x cts# is when its transmitter toggles the input pin (from low to high) during auto cts flow control. x rts# is when its receiver toggles the output pin (f rom low to high) during auto rts flow control. x wake-up indicator is when the uart comes out of sleep mode. 4.4.2 interrupt clearing: x lsr interrupt is cleared by a read to the lsr register. x rxrdy interrupt is cleared by reading data until fifo falls be low the trigger level. x rxrdy time-out interrupt is cleared by reading rhr. x txrdy interrupt is cleared by a read to the isr register or writing to thr. x msr interrupt is cleared by a read to the msr register. x xoff interrupt is cleared by a read to isr or when xon character(s) is received. x special character interrupt is cleared by a read to isr or after the next character is received. x rts# and cts# flow control interrupts are cleared by a read to the msr register. x wake-up indicator is cleared by a read to the isr register.
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 27 ] t able 10: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default) or wake-up indicator isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents ma y be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition) or the device has come out of sleep mode. isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority leve ls (see interrupt source table 10 ). isr[5:4]: interrupt status these bits are enabled when efr bit-4 is set to a logic 1. isr bit-4 indicates that the receiver detected a data match of the xoff character(s). note that once set to a logic 1, the isr bit-4 will stay a logic 1 until a xon character is received. isr bi t-5 indicates that cts# or rts# has changed state. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, set the transm it/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default) ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. logic 0 = no transmit fifo reset (default).
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 28 logic 1 = reset the transmit fifo pointers and fifo leve l counter logic (the transm it shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. x logic 0 = normal operation (default). x logic 1 = dma mode. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = one) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 11 below shows the selections. efr bit-4 must be set to ?1? before these bits can be accessed.note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits 5-4 are associated with these 2 bits. these 2 bits are used to set the trigger level for the receive fifo. the uart will issue a receive in terrupt when the number of the char acters in the fifo crosses the trigger level. table 11 shows the complete se lections. note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side.
t able 11: t ransmit and r eceive fifo t rigger t able and l evel s election t rigger t able b it -5 b it -4 b it -7 b it -6 b it -5 bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility table-a 0 0 0 0 1 1 0 1 0 1 0 0 1 (default) 4 8 14 1 (default) 16c550, 16c2550, 16c2552, 16c554, 16c580 table-b 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 16c650a table-c 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 16c654 table-d 1 1 x x x x programmable via trg register. fctr[7] = 0. programmable via trg register. fctr[7] = 1. 16l2752, 16c2850, 16c2852, 16c850, 16c854, 16c864 xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 29 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 fctr fctr fcr fcr fcr fcr bit-1 bit-0
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 30 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 12 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. t able 12: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0? bit-2
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 31 lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space", low state). this condition remains, unt il disabled by setting lcr bit-6 to a logic 0. x logic 0 = no tx break condition. (default) x logic 1 = forces the transmitter output (tx) to a ?space?, low, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. x logic 0 = data registers are selected. (default) x logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/mod em interface signals or g eneral purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. x logic 0 = force dtr# output high (default). x logic 1 = force dtr# output low. mcr[1]: rts# output the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6 or auto rs-485 half-duplex direction control ou tput enabled by fctr bit-3. if the modem interface is not used, this output may be used as a general purpose output. x logic 0 = force rts# output high (default). x logic 1 = force rts# output low. mcr[2]: reserved op1# is not available as an output pin on the 2751. but it is available for use during internal loopback mode. in the loopback mode, this bit is used to write the state of the modem ri# interface signal. mcr[3]: op2# output / int output enable this bit enables and disables the operation of int/irq#, interrupt output. if int/irq# output is not used, op2# can be used as a general purpose output. also, if 16/68# pin selects motorola bus interface mode, this bit must be set to logic 0 . x logic 0 = int (a-b) outputs disabled (three stat e mode) and op2# output set high (default). x logic 1 = int (a-b) outputs enabled (active mode) and op2# output set low. mcr[4]: internal loopback enable x logic 0 = disable loopback mode (default). x logic 1 = enable local loopback mode, see loopback section and figure 13 . mcr[5]: xon-any enable x logic 0 = disable xon-any function (for 16c550 compat ibility, default). x logic 1 = enable xon-any function. in this mode, any rx character re ceived will resume transmit operation. the rx character will be loaded into the rx fifo, unless the rx characte r is an xon or xo ff character and the 2751 is programmed to use the xon/xoff flow control.
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 32 mcr[6]: infrared encoder/decoder enable x logic 0 = enable the standard modem receive an d transmit input/output interface. (default) x logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. while in this mode, the infrared tx output will be a lo gic 0 during idle data conditions. mcr[7]: brg clock prescaler select the 2751 has a hardware pin (pin 25) to select this function upon power up or reset. after the power up or reset, this register bit will have control and can alter the logic state. x logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). x logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. lsr[0]: receive data ready indicator x logic 0 = no data in receive holding register or fifo (default). x logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun flag x logic 0 = no overrun error. (default) x logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error flag x logic 0 = no parity error (default). x logic 1 = parity error. the receive character in rhr does not have correct pa rity information and is suspect. this error is associated with the char acter available for reading in rhr. lsr[3]: receive data framing error flag x logic 0 = no framing error (default). x logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break flag x logic 0 = no break condition (default). x logic 1 = the receiver received a break signal (rx wa s low for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte.
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 33 lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag x logic 0 = no fifo error (default). x logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears wh en there is no more error(s) in any of the bytes in the rx fifo. 4.9 modem status register (msr) - read only this register provides the current state of the modem interf ace input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag x logic 0 = no change on cts# input (default). x logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag x logic 0 = no change on dsr# input (default). x logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag x logic 0 = no change on ri# input (default). x logic 1 = the ri# input has changed from low to high, ending of the ringing signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag x logic 0 = no change on cd# input (default). x logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow contro l allows starting and stopping of local data transmissions based on the modem cts# signal. a high on the cts# pin will stop uart transmitte r as soon as the current character has finished transmission, and a low will re sume data transmission. normally ms r bit-4 bit is the complement of the cts# input. however in the loopba ck mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the complement of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# input. in the loop back mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used.
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 34 msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.10 scratchpad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the co ntent of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.11 enhanced mode select register (emsr) this register replaces spr (during a write) and is accessible only when fctr[6] = 1. emsr[1:0]: receive/transmi t fifo count (write-only) when scratchpad swap (fctr[6]) is asserted, emsr bits 1-0 controls what mode the fifo level counter is operating in. t able 13: s cratchpad s wap s election fctr[6] emsr[1] emsr[0] scratchpad is 0 x x scratchpad 1 0 0 rx fifo counter mode 1 0 1 tx fifo counter mode 1 1 0 rx fifo counter mode 1 1 1 alternate rx/tx fifo counter mode during alternate rx/tx fifo counter mode, the first value read after emsr bits 1-0 have been asserted will always be the rx fifo counter. the second value read will correspond with the tx fifo counter. the next value will be the rx fifo counter again, then t he tx fifo counter and so on and so forth. emsr[2]: reserved emsr[3]: automatic rs485 half-duplex control output inversion ? logic 0 = rts# output is low during tx and high during rx (default, compatible with 16c2850). ? logic 1 = rts# output is high during tx and low during rx.
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 35 emsr[5:4]: extended rts hysteresis t able 14: a uto rts h ysteresis b it -5 b it -4 b it -1 b it -0 rts# h ysteresis (c haracters ) 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 4 6 8 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 8 16 24 32 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 40 44 48 52 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 12 20 28 36 emsr[6]: lsr interrupt mode ? logic 0 = lsr interrupt dela yed (for 16c2550 compatibilit y, default). lsr bits 2, 3, and 4 will generate an interrupt when the character with the error is in the rhr. ? logic 1 = lsr interrupt immedi ate. lsr bits 2, 3, and 4 will generate an interrupt as soon as the character is received into the fifo. emsr[7]: 16x sampling rate mode logic 0 = 8x sampling rate. logic 1 = 16x sampling rate (for 16c2550 compatibility, default). 4.12 fifo level register (flvl) - read-only the fifo level register replaces the scratchpad register (during a read) w hen fctr[6] = 1. note that this is not identical to the fifo data count register which can be accessed when lcr = 0xbf. flvl[7:0]: fifo level register this register provides the fifo counter level for the rx fifo or the tx fifo or both depending on emsr[1:0]. see table 13 for details. 4.13 baud rate generator registers (dll and dlm) - read/write the concatenation of the contents of dlm and dll gives the 16-bit divisor value which is used to calculate the baud rate: ? baud rate = (clock frequency / 16) / divisor see mcr bit-7 and the baud rate table also. 4.14 device identification register (dvid) - read only this register contains the device id (0x0a for xr16l2 751). prior to reading this register, dll and dlm should be set to 0x00. emsr emsr fctr fctr
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 36 4.15 device revision register (drev) - read only this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00. 4.16 trigger level (trg) - write-only user programmable transmit/receive trigger level register. trg[7:0]: trigger level register these bits are used to program desired trigger levels when trigger table-d is selected. fctr bit-7 selects between programming the rx trigger level (a logic 0) and the tx trigger level (a logic 1). 4.17 fifo data count regi ster (fc) - read-only this register is accessible when lcr = 0xbf. note that this register is not identical to the fifo level count register which is located in the gene ral register set when fctr bit-6 = 1 (scratchpad register swap). it is suggested to read the fifo level c ount register at the scratchpad regist er location when fctr bit-6 = 1. see table 13 . fc[7:0]: rx/tx fifo level count receive/transmit fifo level count. number of characte rs in receiver fifo (fct r[7] = 0) or transmitter fifo (fctr[7] = 1) can be read via this register. 4.18 feature control regi ster (fctr) - read/write this register controls the xr16l2751 new functions. fctr[1:0]: rts hysteresis user selectable rts# hysteresis leve ls for hardware flow control application. after reset, these bits are set to ?0?. see table 14 for more details. fctr[2]: irda rx inversion ? logic 0 = select rx input as encoded irda data (idle state will be low). ? logic 1 = select rx input as inverted en coded irda data (idle state will be high). fctr[3]: auto rs-485 direction control the 2751 has hardware pin 37 to enable this auto rs-485 direction control function from power up, however, pin 37 must be tied to vcc for this bit to gai n control else auto rs-485 is always active. ? logic 0 = standard st16c550 mode. transmitter generates an interrupt when transmit holding register becomes empty and transmit shift register is shifting data out. ? logic 1 = enable auto rs485 direction control function . the direction control signal, rts# pin, changes its output logic state from low to high on e bit time after the last stop bit of the last character is shifted out. also, the transmit interrupt generation is delayed unt il the transmitter shift register becomes empty. the rts# output pin will automatically retu rn to a low when a data byte is loaded into the tx fifo. however, rts# behavior can be inverted by setting emsr[3] = 1. fctr[5:4]: transmit/receive trigger table select see t able 15: t rigger t able s elect b it -5 b it -4 t able 0 0 table-a (tx/rx) 0 1 table-b (tx/rx) 1 0 table-c (tx/rx) 1 1 table-d (tx/rx) table 11 . fctr fctr
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 37 fctr[6]: scratchpad swap ? logic 0 = scratchpad register is selected as general read and write register. st16c550 compatible mode. ? logic 1 = fifo count register (read-only), enhanced mode select register (write-only). number of characters in transmit or receive fifo can be read vi a scratchpad register when this bit is set. enhanced mode select register is select ed when it is written into. fctr[7]: programmable trigger register select ? logic 0 = registers trg and fc selected for rx. ? logic 1 = registers trg and fc selected for tx. 4.19 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 16 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. t able 16: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2, receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2, xoff1 and xoff2
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 38 efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 to be modified. after modifying any enhanced bits, efr bit-4 ca n be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. x logic 0 = modification disable/latch en hanced features. ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings. after a re set, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are set to a logic 0 to be compatible with st16c550 mode (default). x logic 1 = enables the above-mentioned regist er bits to be modified by the user. efr[5]: special character detect enable x logic 0 = special character detect disabled (default). x logic 1 = special character detect enabled. the ua rt compares each incoming receive character with data in xoff-2 register. if a match exists, the receive data will be transfer red to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xo ff1 (efr [1:0]= ?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= ?01?) then flow control works normally, but xoff2 will not go to the fifo, and will g enerate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the pr ogrammed trigge r level and rts de-asserts high at the next upp er trigger level. rts# will return lo w when fifo data falls below the next lower trigger level. the rts# output must be asse rted (low) before the auto rts can take effect. rts# pin will function as a general purpose output when hardware flow control is disabled. x logic 0 = automatic rts flow control is disabled (default). x logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. x logic 0 = automatic cts flow control is disabled (default). x logic 1 = enable automatic cts flow control. data tr ansmission stops when cts# input de-asserts high. data transmission resumes when cts# returns low. 4.20 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the prog rammable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see table 7 .
t able 17: uart reset conditions for channel a and b dlm and dll bits 15-0 = 0x0001. only resets during a power up. it doesn?t reset when the reset pin is asserted. rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff emsr bits 7-0 = 0x80 flvl bits 7-0 = 0x00 efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 fc bits 7-0 = 0x00 i/o signals tx high op2# high rts# high dtr# high rxrdy# high txrdy# low int three-state condition xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 39 registers reset state reset state
absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to 7 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw electrical characteristics typical package thermal resistance data ( margin of error: 15% ) thermal resistance (48-tqfp) theta-ja =59 o c/w, theta-jc = 16 o c/w dc electrical characteristics u nless otherwise noted : ta=0 o to o o to +85 o c for industrial grade package ), v cc =2.25- 5.5v s ymbol p arameter l imits m in m ax l imits m in m ax l imits m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.0 vcc 2.4 vcc 3.0 vcc v v il input low voltage -0.3 0.8 -0.3 0.8 -0.5 0.8 v v ih input high voltage 2.0 5.5 2.0 5.5 2.2 5.5 v v ol output low voltage 0.4 0.4 0.4 v v v i ol = 6 ma i ol = 4 ma i ol = 2 ma v oh output high voltage 1.8 2.0 2.4 v v v i oh = -6 ma i oh = -1 ma i oh = -400 ua i il input low leakage current 10 10 10 ua i ih input high leakage current 10 10 10 ua c in input pin capacitance 5 5 5 pf i cc power supply current 1.2 2 5 ma i sleep i pwrsv sleep current/ powersave current 6 15 30 ua see test 1 xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 40 test 1: the following inputs must rema in steady at vcc or gnd state to mi nimize sleep current: a0-a2, d0-d7, ior#, iow# (r/w#), csa# (cs#), csb# (a3) and all mo dem inputs. also, rxa and r xb inputs must idle at logic 1 state while asleep. floating inputs may result in sleep currents in the ma range. 70 c (-40 2.5v 3.3v 5.0v
xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 41 for powersave, the uart internally isolates all of these inputs (except the modem inputs) therefore eliminating any unnecessary external buffers to keep the inputs steady. see?powersave feature? on page 20. ac electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc =2.25 - 5.5v, 70 p f load where applicable s ymbol p arameter l imits 2.5 m in m ax l imits 3.3 m in m ax l imits 5.0 m in m ax u nit - crystal frequency 16 20 24 mhz clk external clock low/high time 20 15 10 ns osc external clock frequency 24 33 50 mhz t as address setup time (16 mode) 10 10 10 ns t ah address hold time (16 mode) 10 10 10 ns t cs chip select width (16 mode) 150 75 50 ns t rd ior# strobe width (16 mode) 150 75 50 ns t dy read cycle delay (16 mode) 150 75 50 ns t rdv data access time (16 mode) 135 70 45 ns t dd data disable time (16 mode) 0 45 0 30 0 30 ns t wr iow# strobe width (16 mode) 150 75 50 ns t dy write cycle delay (16 mode) 150 75 50 ns t ds data setup time (16 mode) 25 20 15 ns t dh data hold time (16 mode) 15 10 10 ns t ads address setup (68 mode) 10 10 10 ns t adh address hold (68 mode) 10 10 10 ns t rws r/w# setup to cs# (68 mode) 10 10 10 ns t rda read data access (68 mode) 135 70 45 ns t rdh read data disable (68 mode) 45 30 30 ns t wds write data setup (68 mode) 25 20 15 ns t wdh write data hold (68 mode) 15 10 10 ns t rwh cs# de-asserted to r/ w# de-asserted (68 mode) 15 10 10 ns t csl cs# width (68 mode) 150 75 50 ns t csd cs# cycle delay (68 mode) 150 75 50 ns
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 42 t wdo delay from iow# to output 150 75 50 ns t mod delay to set interrupt from modem input 150 75 50 ns t rsi delay to reset interrupt from ior# 150 75 50 ns t ssi delay from stop to set interrupt 1 1 1 bclk t rri delay from ior# to reset interrupt 150 75 50 ns t si delay from stop to interrupt 150 75 50 ns t int delay from initial int reset to transmit start 8 24 8 24 8 24 bclk t wri delay from iow# to reset interrupt 150 75 50 ns t ssr delay from stop to set rxrdy# 1 1 1 bclk t rr delay from ior# to reset rxrdy# 150 75 50 ns t wt delay from iow# to set txrdy# 150 75 50 ns t srt delay from center of start to reset txrdy# 8 8 8 bclk t rst reset pulse width 40 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x or 8x of data rate hz f igure 14. c lock t iming osc clk clk external clock ac electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc =2.25 - 5.5v, 70 p f load where applicable s ymbol p arameter l imits 2.5 m in m ax l imits 3.3 m in m ax l imits 5.0 m in m ax u nit
f igure 15. m odem i nput /o utput t iming f or c hannels a & b iow # iow rts# dtr# cd# cts# dsr# int ior# ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active f igure 16. 16 m ode (i ntel ) d ata b us r ead t iming t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# ior# d0-d7 rdtm t cs t rd xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 43
f igure 17. 16 m ode (i ntel ) d ata b us w rite t iming 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# iow# d0-d7 t cs t wr f igure 18. 68 m ode (m otorola ) d ata b us r ead t iming 68read t ads t rdh t adh t csl t rda t csd t rws valid address valid address valid data a0-a2 cs# r/w# d0-d7 t rwh valid data xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 44
f igure 19. 68 m ode (m otorola ) d ata b us w rite t iming 68write t ads t adh t csl t wds t csd t rws valid address valid address valid data a0-a2 cs# r/w# d0-d7 t rwh valid data t wdh f igure 20. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 45
f igure 21. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 46
f igure 23. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when tx fifo fills up to the trigger level. xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 47
f igure 25. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b tx txrdy# iow# int* d0:d7 s txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri t (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level at least 1 empty location in fifo t srt tx fifo full t wt t si isr read isr read *int cleared when the isr is read or when tx fifo fills up to trigger level. ier[1] enabled xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 48
package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c note: the control dimension is the millimeter column a 0.039 0.047 1.00 1.20 a 1 0.002 0.006 0.05 0.15 a 2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d 1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 xr16l2751 rev. 1.2.3 2.25v to 5.5v duart with 64-byte fifo and powersave 49 inches millimeters symbol min max min max
xr16l2751 2.25v to 5.5v duart with 64-byte fifo and powersave rev. 1.2.3 50 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2010 exar corporation datasheet april 2010. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. revision history d ate r evision d escription november 2001 rev p1.0.0 prelim data sheet. march 2002 rev p1.1.0 corrected int output descriptions and reset state. clarified mcr bit-3 description. added 68 mode (motorola) data bus timing specs. renamed sclk to bclk. changed a0-a7 in figures 16 through 19 to a0-a2. september 2002 rev 1.0.0 release into production. clarified rts# pin descriptions, xtal1 pin description, external clock description, auto rs485 half-duplex control description, emsr bit-3 description and updated 2.5 v, i cc and i sleep dc electrical characteristics. march 2003 rev 1.1.0 updated ac electrical characteristics. august 2004 rev 1.2.0 added device status to ordering information. clarified pin descriptions- changed from using logic 1 and logic 0 to high (vcc) and low (gnd) for input and output pin descriptions. april 2005 rev 1.2.1 updated the data access times (t rdv and t rda ) in ac electrical characteristics. october 2005 rev 1.2.2 clarified wake-up indicator interrupt in sleep mode description in ?section 2.20, sleep mode with wake-up indicator and powersave feature? on page 20 and ?section 4.4, interrupt status register (isr) - read-only? on page 26 . april 2010 rev 1.2.3 corrected auto rs-485 half duplex direction control feature. it does not support turn- around delay.

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